As the complexity of integrated circuits has continued to increase, the cost of fabrication of each individual integrated circuit has also increased. This is particularly true for complicated integrated circuits such as large memories and microprocessors. The cost of fabricating integrated circuits is a result of the fact that integrated circuit fabrication requires multiple complicated steps, significant amounts of special and expensive material, and very expensive and highly specialized equipment to apply the materials in precisely formed and etched layers.
In order to ensure a return on the investment of time, materials, and capital, required to produce each integrated circuit, it is important that a relatively large percentage of the integrated circuits created perform as expected without defects or flaws. However, because the fabrication of integrated circuits can be so complex, and because the process is so susceptible to contamination, thermal effects, and physical stress of any kind, defects are always present and there is often a significant number of defective integrated circuits fabricated that are simply non-usable. When this is the case, absent some other repair mechanism, all of the time, materials and investment made in the defective integrated circuits are simply wasted. The ratio of operational integrated circuits produced to total integrated circuits produced is called the yield of the process.
As a way of increasing the yield of a given process, many integrated circuit designers and manufacturers include special redundant “repair” circuitry that is formed at strategic locations on the integrated circuit. The purpose of the repair circuits is to provide redundant capability on the integrated circuit chip that can be accessed to replace circuitry and subsystems that fail to operate as specified. Consequently, using repair circuitry blocks, a failure of a single circuit or functional block of the integrated circuit does not necessitate throwing away the entire chip and starting over. Instead, the damaged portion of the integrated circuit can be bypassed and the repair circuitry accessed to take its place. This means that the integrated circuit can be salvaged and all of the resources used to create the integrated circuit can be saved. Of course, to effectively use the repair circuitry it is important that the defect be discovered as early as possible and under as realistic integrated circuit operational conditions as possible. Use of repair circuit blocks is well known in the art and has proven very effective at increasing process yield and keeping the cost of fabrication down.
In the prior art, one method for accessing the repair circuitry when it was needed was to include fuses that were either annealed (melted) or blown (ablated), collectively referred to herein as activated, to make or break electrical connections, provide access to the repair circuitry, and by-pass the faulty circuitry. In many instances, the fuses were annealed or blown by using LASER energy.
FIG. 1A shows a simplified perspective view of an integrated circuit chip 100. Integrated circuit chip 100 has an active side 111 and a backside 112. Active side 111 of integrated circuit chip 100 includes active surface 107 in which, and on which, the circuitry of integrated circuit chip 100 is formed. As shown in FIG. 1A active surface 107 lies in the plane 101 formed by axis 131, the Y-axis, and axis 133, the X-axis. As also shown in FIG. 1A, axis 135, the Z-axis, extends through integrated circuit chip 100 from active surface 107 to backside 112. A poly or other passivation layer 141 is formed over active surface 107 to protect active surface 107 from contamination and other environmental factors. Both passivation layer 141 and active surface 107 are situated on a substrate 103, typically silicon. Substrate 103, and therefore integrated circuit chip 100, also includes a backside surface 105.
FIG. 1B is overhead view of plane 101 formed by axis 131, the Y-axis, and axis 133, the X-axis, active side 111 of integrated circuit chip 100, and the various circuitry formed in active surface 107 including redundant repair circuitry block 110 and a LASER activated fuse 130 for electrically connecting redundant repair circuitry block 110 when it is needed.
According to prior art teachings, LASER activated fuses, such as LASER activated fuse 130, had to be activated, i.e., either annealed or blown, from active side 111 of integrated circuit chip 100 so that an optical path could be guaranteed for the LASER energy to access and focus on LASER activated fuse 130. FIG. 2 shows a simplified process for activating a LASER activated fuse, such as LASER activated fuse 130, as was necessitated by the prior art teachings. As shown in FIG. 2, an opening 253 in passivation layer 141 was required in the prior art to give LASER energy 251 from LASER 250 optically clear access to LASER activated fuse 130 on active surface 107 of active side 111 of integrated circuit 100.
In the prior art, LASER activated fuses could only be activated from the active side 111 of integrated circuit chip 100. This was because LASER energy 251 was typically generated such that LASER energy 251 was absorbed by substrate material 103, typically silicon. As a result, LASER energy 251 had to focus on a point, such as LASER activated fuse 130, located in the plane 101 formed by axis 131, the Y-axis, and axis 133, the X-axis (FIG. 1A and FIG. 1B). Consequently, in the prior art, LASER energy 251 had to have optically clear access to LASER activated fuse 130 on active surface 107 of active side 111 of integrated circuit 100. Importantly, using prior art methods, LASER activated fuse 130 could not be activated by LASER energy 251 from LASER 250 from backside 112 and backside surface 105 of integrated circuit 100 because the LASER energy 251 would be absorbed by substrate 103 of integrated circuit chip 100 and could not penetrate substrate 103 with any certainty or accuracy, or without creating unacceptable damage to substrate 103.
While using the prior art methods to activate LASER activated fuse 130 allowed many otherwise non-functional integrated circuit chips 100 to be repaired, the fact that, using prior art methods, LASER activated fuse 130 could not be activated by LASER energy 251 from backside 112 and backside surface 105 of integrated circuit 100 was a distinct disadvantage for several reasons. First, a large percentage of integrated circuits are now packaged using the well-known “flip-chip” mounting procedure wherein the active side 111 of integrated circuit chip 100 faces a mounting substrate and therefore active side 111, and LASER activated fuse 130, is not accessible once integrated circuit 100 is operationally mounted.
FIG. 3 shows a simplified flip-chip configuration of integrated circuit chip 100. As shown in FIG. 3, when mounted in a flip-chip configuration, active side 111 of integrated circuit chip 100 includes solder mounting bumps 303 that are coupled to mounting pads 305 that are formed on first surface 307 of mounting substrate 301. Mounting Pads 305 are, in turn, coupled to connection pads 309 on second surface 312 of mounting substrate 301. Connection pads 309 are then used to couple the structure of FIG. 3 to a motherboard or other larger unit. Flip-chip mounting of integrated circuits is well known to those of skill in the art. Consequently, a more detailed discussion of flip-chip mounting is excluded here to avoid detracting from the present invention.
Importantly, as shown in FIG. 3, once integrated circuit chip 100 is flip-chip mounted to mounting substrate 301, i.e., once integrated circuit chip 100 is operationally connected as it will be used in the field, there is no optically direct access to active side 111 of integrated circuit chip 100 or to active surface 107 and LASER activated fuse 130. Consequently, using prior art methods, LASER activated fuse 130 could not be activated once integrated circuit chip 100 was connected as it would be deployed. This meant that integrated circuit chip 100 could not be tested under its actual operating conditions and that special test equipment had to be used to try to find defects prior to mounting integrated circuit chip 100 because post-mounting defects could not be corrected, at least not without un-mounting and then re-mounting integrated circuit chip 100. Of course, un-mounting and then re-mounting integrated circuit chip 100 was very expensive and often resulted in causing more damage to integrated circuit chip 100 and/or introduced more contamination to the unit. In addition, with Multi-Chip Modules (MCMs) the process was even more burdensome and inefficient.
Testing integrated circuit chip 100 prior to mounting integrated circuit chip 100 in a flip-chip configuration meant that integrated circuit chip 100 could typically not be observed under realistic operating conditions, i.e., at realistic speeds and under realistic operating thermodynamics, since the actual connections that would be used in the field would not have been made and integrated circuit chip 100 would not be in its integrated circuit package.
In addition, testing integrated circuit chip 100 prior to mounting integrated circuit chip 100, as required by the prior art methods, meant that any contamination and/or defects from the packaging/mounting process would be introduced after testing and could not be repaired. Consequently, in this event, not only would the cost of integrated circuit chip 100 be wasted but the cost of further testing and processing of integrated circuit chip 100 and the packaging of integrated circuit chip 100 would also be wasted.
In addition, as noted above, testing integrated circuit chip 100 prior to mounting integrated circuit chip 100, as required in the prior art, meant the purchase and use of special test equipment (not shown) that could make temporary signal connections and at least partially test integrated circuit chip 100 to try to find defects prior to mounting. To make matters worse, connecting and disconnecting integrated circuit chip 100 to the special test equipment could itself cause damage to integrated circuit chip 100 or introduce contamination.
In short, using prior art methods, it was possible that an integrated circuit chip, such as integrated circuit chip 100, would be at least partially tested prior to flip-chip mounting and a defect could be found and even repaired using the prior art LASER methods described above prior to mounting. Using prior art methods, the integrated circuit chip could then be mounted and packaged only to find that a defect, either undetected under the simulated conditions of the test equipment, or created during the testing/mounting/packaging process, was present and could not be repaired because there was no active side access to the integrated circuit. Consequently, all the time, materials and energy involved in making the integrated circuit chip, making the repair circuitry, testing the integrated circuit chip, repairing a first defect in the integrated circuit chip and packaging the integrated circuit chip would be wasted. In this instance, the manufacturer would have been better off not having repair circuits and simply discarding the integrated circuit chip when the first error was found in order to cut losses.
As discussed above, the fact that, using prior art methods, once integrated circuit chip 100 was flip-chip mounted to mounting substrate 301, i.e., once integrated circuit chip 100 was operational connected as it would be used, LASER activated fuse 130 could not be activated meant that many of the advantages of having repair circuitry 110 in the first place were negated, and that many otherwise repairable integrated circuits 100 were wasted because they could not be repaired after mounting. This was particularly unfortunate because flip-chip mounting has become very commonplace, both to package individual integrated circuits 100 and in MCMs. In addition, when MCMs are employed, the individual integrated circuit chips making up the MCM must electrically communicate with each other for proper unit operation. However, using prior art methods, the integrated circuits chips had to be tested individually prior to mounting in the MCM. Consequently, not only was there an inability to test the integrated circuit chips under operation conditions, but a failure of one chip meant that multiple integrated circuit chips, and all the resources expended to make them and the MCM package, could potentially be wasted.
What is needed is a method for activating LASER activated fuses from the backside of an integrated circuit thereby allowing activation of LASER activated fuses after an integrated circuit chip is flip-chip and/or MCM mounted.